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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public archive

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Repositories

Showing 10 of 112 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 21 Apache-2.0 40 120 (7 issues need help) 27 Updated Feb 2, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 136 Apache-2.0 84 222 (12 issues need help) 83 Updated Feb 2, 2026
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,558 Apache-2.0 647 350 (1 issue needs help) 140 Updated Feb 2, 2026
  • caliptra-dpe Public

    High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

    chipsalliance/caliptra-dpe’s past year of commit activity
    Rust 20 Apache-2.0 29 19 10 Updated Feb 2, 2026
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 308 Apache-2.0 44 18 29 Updated Feb 2, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 43 Apache-2.0 20 17 3 Updated Feb 2, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 41 757 0 0 Updated Feb 2, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 7 6 0 0 Updated Feb 2, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 127 Apache-2.0 75 102 (2 issues need help) 27 Updated Jan 31, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 357 ISC 86 47 (4 issues need help) 29 Updated Jan 30, 2026
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